Instead of having the FPGA in the external device, one could replace it with a microcontroller that stuffs the data into packets to be sent raw over Gigabit Ethernet. On the other side of the intertube then exists whatever solution one decides is appropriate to handle the massive flow of data, such as one of these:
http://www.picocomputing.com/
This should have the added benefit of decreasing the noise present at the ADC, and decreasing the power requirements. With Power over Ethernet, the device could be very simple. And cheap.
The ADC should probably do no more than a little over 60 million samples per second at 12 bits per sample, and be strongly capable of undersampling.
Between the ADC and the analogue signal source must exist an amplifier, bandpass filter, and possibly a dynamic range compressor or limiter to deal with strong signals. A modular design should allow for cost saving. These are all traditional radio design issues, so an elegant solution should already exist.
Thursday, December 6, 2007
Tuesday, March 6, 2007
High-speed ACDs and FPGAs for dummies
This is a must-see.
http://www.national.com/nationaltv/
Bob Pease's Analog by Design show covered High-Speed Data Transfers in two parts, and thus gives an excellent outline of the topics I need to study.
Henry Vredegoor posts to the GNU Radio mailing list informing me about this project;
http://wwwhome.cs.utwente.nl/~ptdeboer/ham/sdr/#jun2006
I'm going to contact PA3FWM, asking him if he's willing to share his secrets. ;)
Further, Brian Padalino is providing me with genuine insight into these through the GNU Radio list.
With all this info coming to me I'm beginning to feel truly spolied! Hehe.
http://www.national.com/nationaltv/
Bob Pease's Analog by Design show covered High-Speed Data Transfers in two parts, and thus gives an excellent outline of the topics I need to study.
Henry Vredegoor posts to the GNU Radio mailing list informing me about this project;
http://wwwhome.cs.utwente.nl/~ptdeboer/ham/sdr/#jun2006
I'm going to contact PA3FWM, asking him if he's willing to share his secrets. ;)
Further, Brian Padalino is providing me with genuine insight into these through the GNU Radio list.
With all this info coming to me I'm beginning to feel truly spolied! Hehe.
Monday, March 5, 2007
Some specifics about ADCs and projects specs
Posted this to the discuss-gnuradio mailing list, but it should be here too:
I suspect the best design method would be to look at the most expensive issues first, make those cheaper and then design the rest around that. The FPGA, ADC and PCB seem to be the most expensive parts right now. I can't say anything about the PCB yet, but the dimensioning of the ADC and FPGA would be an issue of what we can get away with and still have an SDR. The dimensioning of the FPGA depends on the ADC, so the ADC should be the first issue to be dealt with.
A high SINAD and SNR value for the ADC seems to be important at any rate, regardless of bit-count, but those values still seem to be proportional to how many bits of accuracy it has. Low jitter is apparently also important.
The LTC1742 seems attractive in that regard and the price isn't that terrible either, but it's a 14bit device. The ADC12C065 and ADC12DS065 are 12 bits, but I don't know National's price on those. They seem to support undersampling up to 1GHz. If we could use that, we'd have a pretty awesome radio.
Analog Devices' AD9235 is really cheap and seems to support undersampling to 500MHz, which is pretty cool too. More than I need at any rate.
There are of course other manufacturers to consider, but I feel this is a good start at the very least. Gives an idea what we're dealing with.
I think the step after deciding on the ADC would be to dimension the FPGA by deciding what code it needs to run. It will have to deal with a bit of Ethernet, and stuffing all the data from the ADC into the frames. Of course that's not all, but right now it seems that will be its most taxing task, so it should be spec-ed to be able to deal with that. I have no idea what those specs are. Guess I'll have to learn Verilog before I can start guesstimating.
I suspect the best design method would be to look at the most expensive issues first, make those cheaper and then design the rest around that. The FPGA, ADC and PCB seem to be the most expensive parts right now. I can't say anything about the PCB yet, but the dimensioning of the ADC and FPGA would be an issue of what we can get away with and still have an SDR. The dimensioning of the FPGA depends on the ADC, so the ADC should be the first issue to be dealt with.
A high SINAD and SNR value for the ADC seems to be important at any rate, regardless of bit-count, but those values still seem to be proportional to how many bits of accuracy it has. Low jitter is apparently also important.
The LTC1742 seems attractive in that regard and the price isn't that terrible either, but it's a 14bit device. The ADC12C065 and ADC12DS065 are 12 bits, but I don't know National's price on those. They seem to support undersampling up to 1GHz. If we could use that, we'd have a pretty awesome radio.
Analog Devices' AD9235 is really cheap and seems to support undersampling to 500MHz, which is pretty cool too. More than I need at any rate.
There are of course other manufacturers to consider, but I feel this is a good start at the very least. Gives an idea what we're dealing with.
I think the step after deciding on the ADC would be to dimension the FPGA by deciding what code it needs to run. It will have to deal with a bit of Ethernet, and stuffing all the data from the ADC into the frames. Of course that's not all, but right now it seems that will be its most taxing task, so it should be spec-ed to be able to deal with that. I have no idea what those specs are. Guess I'll have to learn Verilog before I can start guesstimating.
Ideas about features
The features I've so far taken liking of are;
The ICs and other components should be possible to get for below $100€. The PCB I'm not sure about. The HPSDR project sells theirs through TAPR for $10 to $30, so it looks promising.
I have no economical means to make a bigger batch of these boards if they ever become more than an idea, but maybe TAPR and others would be interested.
The CPU will have a lot to deal with, and I doubt processors much below 3GHz 4P equivalent would deliver good performance. With some software maturity it might however be possible to do fewer unnecessary things and thus still deliver good SDR performance on ~2GHz P4 equiv. machines.
Once, if ever, the hardware platform is "done", I'd like to begin developing strange and curious ways to deal with all this data that drops in from the aether. Hm. Aether... Should develop a nice play of words on that to name the hardware by.
- Price below $100€
- Direct-sampling of signals using high-speed ADC
- No decimation of data. Everything goes to the CPU
- Gigabit Ethernet link
- FPGA to do the magic between the ADC and GE link
- Possibility to develop the use of undersampling by the ADC
- Connector to accommodate for HPSDR Gibraltar-like clock and Tx capability, to be developed later
The ICs and other components should be possible to get for below $100€. The PCB I'm not sure about. The HPSDR project sells theirs through TAPR for $10 to $30, so it looks promising.
I have no economical means to make a bigger batch of these boards if they ever become more than an idea, but maybe TAPR and others would be interested.
The CPU will have a lot to deal with, and I doubt processors much below 3GHz 4P equivalent would deliver good performance. With some software maturity it might however be possible to do fewer unnecessary things and thus still deliver good SDR performance on ~2GHz P4 equiv. machines.
Once, if ever, the hardware platform is "done", I'd like to begin developing strange and curious ways to deal with all this data that drops in from the aether. Hm. Aether... Should develop a nice play of words on that to name the hardware by.
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